commit c5dd46ed1f6beb5ad731bce017f4bc0720e8797e
parent 4a1ab8949295039f01c641d8a96eebdc9328073e
Author: Ryan Jeffrey <ryan@ryanmj.xyz>
Date: Thu, 27 Oct 2022 11:18:19 -0700
New readme
Diffstat:
2 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/README.org b/README.org
@@ -3,14 +3,31 @@
#+EMAIL: ryan@ryanmj.xyz
#+OPTIONS: num:nil
-An emulated PC with a RISC II processor.
+* What
+An emulated PC with a RISC II processor. See [[https://ryanmj.xyz/riscii][this page]] for an in-depth
+description of the RISC II processor.
+
+The RISC II was an experimental processor created at UC Berkeley by
+Manolis Katevenis and Robert Sherburne under professors David
+Patterson and Carlo Séquin. It was completed in 1983 as the successor
+to the original RISC processor. It had a simple design with 32 bit
+instructions, only two instruction formats, and only two addressing modes.
+The RISC II served as the primary inspiration for the Sun SPARC
+architecture, an early industry implementation of RISC.
+
+Documentation on the RISC II is scarce and its technical details can
+only be found in Katevenis' PhD thesis. This project exists to
+preserve knowledge on this important piece of computer history.
+
+See [[https://github.com/Ma11ock/riscii-guy][this project]] for an experimental assembler for the RISC II.
** Feature completeness
-- [ ] RISC II emulation
-- [ ] SDL window, I/O, sound
-- [ ] MMU
-- [ ] Firmware (probably IEEE 1275) implementation
-- [ ] Floating point co processor
-- [ ] Multicore
+| Feature | State |
+|-----------------------------------+------------------------------|
+| RISC II instruction set emulation | Partial [fn::There are bugs] |
+| Screen output & I/O | Work started |
+| MMU/Virtual Memory | No |
+| Firmware | No |
+
diff --git a/riscii.org b/riscii.org
@@ -1088,7 +1088,8 @@ address currently being accessed.
** Destination latch (32 bits)
<<sec:dest_latch>> Where the result of an instruction is stored until
it is written to the destination register during the next
-instruction. The
+instruction. It is connected to the ALU, shifter, PSW, PC's, and the
+register file.
** Data/In and Immediate latch (DIMM) (32 bits)
<<sec:dimm>> Combined Data/In and immediate latch. It is attached
to a dedicated sign extender.
@@ -1217,8 +1218,6 @@ out of register windows on a function call it must flush the oldest
window(s) to memory and then restore them when the current function
returns.
-** Processor Status Word
-<<sec:psw>>
** Special registers
<<sec:spec>> The RISCII's pipeline also has five special registers
used for internal state.
